An Optimal Gate Design for the Synthesis of Ternary Logic Circuits

Department of Electrical EngineeringOver the last few decades, CMOS-based digital circuits have been steadily developed. However, because of the power density limits, device scaling may soon come to an end, and new approaches for circuit designs are required. Multi-valued logic (MVL) is one of the new approaches, which increases the radix for computation to lower the complexity of the circuit. For the MVL implementation, ternary logic circuit designs have been proposed previously, though they could not show advantages over binary logic, because of unoptimized synthesis techniques. In this thesis, we propose a methodology to design ternary gates by modeling pull-up and pull-down operations of the gates. Our proposed methodology makes it possible to synthesize ternary gates with a minimum number of transistors. From HSPICE simulation results, our ternary designs show significant power-delay product reductions; 49 % in the ternary full adder and 62 % in the ternary multiplier compared to the existing methodology. We have also compared the number of transistors in CMOS-based binary logic circuits and ternary device-based logic circuits We propose a methodology for using ternary values effectively in sequential logic. Proposed ternary D flip-flop is designed to normally operate in four-edges of a ternary clock signal. A quad-edge-triggered ternary D flip-flop (QETDFF) is designed with static gates using CNTFET. From HSPICE simulation results, we have confirmed that power-delay-product (PDP) of QETDFF is reduced by 82.31 % compared to state of the art ternary D flip-flop. We synthesize a ternary serial adder using QETDFF. PDP of the proposed ternary serial adder is reduced by 98.23 % compared to state of the art design.ope

Ternary full adder using multi-threshold voltage graphene barristors

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10-16 J, which is comparable with the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors

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Department of Electrical EngineeringBinary logic circuits have been the basis for modern computers to improve energy efficiency based on complementary metal-oxide-semiconductor (CMOS) technology. However, as the limitations of CMOS scaling are approaching, a new computing paradigm has been required. Multi-valued logic (MVL) circuits focus on minimizing hardware cost by processing more than two values per elementary operation. In recent years, various designs of three-valued (ternary) logic circuits have been proposed as the first step toward implementing MVL circuits with emerging technologies. The MVL is expected to improve the energy efficiency of digital circuits because fewer logic gates and interconnects are required than binary logic for the same function by calculating multiple values in a logic gate. In this paper, I propose an efficient design methodology for various ternary logic circuits using emerging technologies to demonstrate the potential of a ternary microprocessor. A logic synthesis methodology is proposed with a novel low-power circuit structure for ternary logic. Various arithmetic logic circuits for balanced and unbalanced ternary logic are designed, including ternary logic gates (STI, NMIN, NMAX), half adder, full adder, multiplier, latch, flip-flop (FF), static random-access memory (SRAM), binary to ternary (B2T) converter, ternary to binary converter (T2B), and ternary digital to analog converter (T-DAC). This study is expected to accelerate the implementation of ternary microprocessors using emerging technologies, and MVL is expected to attract attention as a new computing paradigm.clos

Memcapacitor based Minimum and Maximum Gate Design

In this paper, we suggest a new structure of complementary capacitive switch that is composed of two connected memcapacitors. We also propose MIN and MAX gates that use this structure. HSPICE simulation verified the behavior of these logic gates for a specific input pattern. The functionality of each logic gate was verified even for analog signal processing, and these logic gates will be useful in fuzzy logic processing.1

A novel design methodology for error-resilient circuits in near-Threshold computing

Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the reliability of NTC operations, error-resilient techniques are indispensable, though they cause area and power overheads. In this paper, we propose a design methodology which provides an optimal implementation of error-resilient circuits. A modified Quine-McCluskey (Q-M) algorithm is exploited to earn the minimum set of error-resilient circuits without any loss of detection ability. From the proposed design flow, benchmark results show that optimal design reduces up to 72% of required flip-flops to be changed to error-resilient circuits without compromising an error detection ability

Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm

Logic synthesis has been increasingly important to accelerate the development of high-level systems. However, in multi-valued logic, logic synthesis methods that can process emerging devices are deficient. We propose and automate a method to synthesize ternary logic circuits. Our design of ternary logic circuits is based on static gate design, and exploits carbon nanotube field-effect transistors. We optimize ternary logic circuits by minimizing the number of transistors with a modified Quine-McCluskey algorithm. Our proposed method has improved power-delay product by 52.72 % over the state-of-the-art method for a ternary half adder, and by 68.06 % for a ternary multiplier. We also have improved power-delay product by 37.30 % over the state-of-the-art method for a ternary full adder that has high load capacitance. Our design has an average of 42.43 % fewer transistors than the existing design for circuits that have large number of inputs. As circuits become larger, the improved power-delay product and reduced transistor count are advantageous

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion

A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-Trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.1

Design and analysis of a low-power ternary SRAM

This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89µA to 1.46µA. By connecting ternary inverters back-to-back, a tritstorage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.1

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

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MTCMOS-based Ternary to Binary Converter

Ternary logic circuits can reduce circuit power consumption and interconnections. We propose a ternary to binary converter that uses multi-threshold CMOS (MTCMOS) for energy-efficient logic converting to use these benefits. We reduce the delay by 8.61%, power by 28.72% compared to the previous design. We also reduce area, and the number of transistors compared to the existing converter design.1